EDN

FPGA-to-ASIC conversion a crucial concern

It is clear that FPGAs are great for prototyping and low-volume production. It's also clear, however, that any relatively complex mid- to high-volume design for which power consumption, component cost ...
Design And Reuse

Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology

Antipolis, France — Presto Engineering Group, a global leader in application-specific integrated circuit (ASIC) supply and semiconductor services, and Menta, a pioneer and recognized leader in ...
Business Wire

Faraday Unveiled FPGA-Go-ASIC Prototyping Platform to Accelerate FPGA-to-ASIC Conversion

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today unveiled its FPGA-Go-ASIC™ prototyping platform solution. This ...
AV Network

Justin Kennington on AV Supply Chain Using FPGA vs. ASIC Chips

SDVoE Alliance President, Justin Kennington shares his perspective on how FPGA versus ASIC chips impacts the product supply chain in the AV industry. When you purchase through links on our site, we ...
EDN

FPGA or ASIC?

Gary Meyers, president and CEO of FPGA tool vendor Synplicity, sat down with Electronic News to talk about what’s changing in the EDA industry. What follows are excerpts of that conversation. Meyers: ...
New Electronics

Presto Engineering and Menta partner to advance adaptable semiconductor design

Presto Engineering and Menta collaborate on accelerating the development of adaptive semiconductor architectures.
Electronic Design

Faraday Showcases FPGA-Go-ASIC, SONOS eFlash, and eFPGA Solutions

This article appeared in Microwaves & RF and has been published here with permission. Check out our Design Automation Conference 2023 coverage. Faraday Technology comes to Booth 2343 at DAC to discuss ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Digi Times

FPGA vs ASIC: Altera CEO highlights FPGA's advantage in AI era

Embedded World 2025 officially commenced this week in Nuremberg, Germany, with Sandra Rivera, CEO of FPGA company Altera, delivering the keynote address. In her presentation, Rivera discussed key ...
Hackaday

Your Own Open Source ASIC: SkyWater-PDK Plans First 130 Nm Wafer In 2020

You might have caught Maya Posch’s article about the first open-source ASIC tools from Google and SkyWater Technology. It envisions increased access to make custom chips — Application Specific ...
Business Weekly

Cambridge startup Signaloid tapes out C0-ASIC, delivering 1000x energy savings for AI

Signaloid, a Cambridge computing platform company providing hardware and binary-translation-based acceleration of AI, ...