Semiconductor Engineering

External Resistance Reduction By Nanosecond Laser Anneal In Si/SiGe CMOS Technology

We report on a significant pFET external resistance reduction (~40%) and corresponding 10% RON decrease by nanosecond laser annealing of S/D structures applicable to advanced technology nodes.
Electronic Design

Solving the contact resistance challenge for 7nm and beyond CMOS

With the development of novel titanium-silicidation techniques, imec Ph.D. student Hao Yu presents improved source/drain contact schemes which help solving the contact resistance challenge for ...
EDN

STMicro uses ‘pure’ CMOS approach in read-channel IC for higher integration

GENEVA–STMicroelectronics today announced samples of a new CMOS read/write channel chip that supports data rates up to 750 megabits per second and features advanced signal processing techniques for ...
Electronic Design

GaN Transistors – Drive Control, Thermal Management, and Isolation

This year, several companies are expected to bring 600/650 V Gallium Nitride (GaN) power transistors to market. Almost all will be normally-on (depletion mode) transistors connected in a cascode ...
EDN

1-Channel 150 mA CMOS LDO Regulators

ROHM offers a wide lineup of general-purpose 3-pin regulators featuring low power consumption, high current capability, and high voltage resistance. ROHM’s LDO’s are ideal for mobile phones, ...